1. Field of the Invention
The present invention relates to a semiconductor capacitor structure, and more particularly, to a metal-insulator-metal (MIM) type capacitor structure.
2. Description of the Prior Art
In semiconductor manufacturing processes, metal capacitors constituted by metal-insulator-metal (MIM) type capacitor structure are widely applied in Ultra Large Scale Integration (ULSI) designs. Due to its lower resistance, less significant parasitic effect, and absence of induced voltage shift in the depletion region, metal capacitors with MIM type structure are usually adopted as the main choice of semiconductor capacitor designs.
Applications of interdigitated metal capacitors have already been disclosed and discussed in various literatures, such as U.S. Pat. No. 6,784,050, U.S. Pat. No. 6,885,543, U.S. Pat. No. 6,974,744, U.S. Pat. No. 6,819,542, and Taiwan Patent No. 222,089 (the Taiwan patent of U.S. Pat. No. 6,819,542), etc., whose contents are incorporated herein by reference.
In U.S. Pat. No. 6,819,542, a multilevel interdigitated metal structure is defined, wherein the multilevel interdigitated metal structure includes at least a plurality of odd layers, a plurality of even layers, and a plurality of dielectric layers. The plurality of odd layers and the plurality of even layers comprise a first electrode and a second electrode. The first electrode in the plurality of odd layers is coupled to the first electrode in the plurality of even layers through a first bus. The second electrode in the plurality of odd layers is coupled to the second electrode in the plurality of even layers through a second bus.
In U.S. Pat. No. 6,819,542 (hereinafter “the '542 patent”), a multilevel interdigitated metal structure is defined. Please refer to FIG. 1 and FIG. 2. FIG. 1 is a diagram of an odd layer 10 of a multilevel interdigitated metal structure as shown in FIG. 5B of the '542 patent. FIG. 2 is a diagram of an even layer 20 of a multilevel interdigitated metal structure as shown in FIG. 6B of the '542 patent.
Please first refer to FIG. 1. The odd layer 10 comprises a first electrode 11 and a second electrode 15. The first electrode 11 includes a first section 12, and a plurality of second sections 13 arranged in parallel. The first section 12 includes a first portion 12A and a second portion 12B. The first portion 12A and the second portion 12B respectively constitute the two strokes of the L-shaped first section 12. The plurality of parallel-arranged second sections 13 join the first portion 12A of the first section 12, and separate from one another by a predetermined distance. The second electrode 15 includes a first section 16, and a plurality of second sections 17 arranged in parallel. The first section 16 includes a first portion 16A and a second portion 16B. The first portion 16A and the second portion 16B respectively constitute the two strokes of the L-shaped first section 16. The plurality of parallel-arranged second sections 17 join the first portion 16A of the first section 16, and separate from one another by a predetermined distance. The plurality of second sections 13 of the first electrode 11 and the plurality of second sections 17 of the second electrode 15 interdigitate in parallel.
Please now refer to FIG. 2. The even layer 20 includes a first electrode 21 and a second electrode 25. The first electrode 21 includes a first section 22, and a plurality of second sections 23 arranged in parallel. The first section 22 includes a first portion 22A and a second portion 22B. The first portion 22A and the second portion 22B respectively constitute the two strokes of the L-shaped first section 22. The plurality of parallel-arranged second sections 23 join the first portion 22A of the first section 22, and separate from one another by a predetermined distance. The second electrode 25 includes a first section 26, and a plurality of second sections 27 arranged in parallel. The first section 26 includes a first portion 26A and a second portion 26B. The first portion 26A and the second portion 26B respectively constitute the two strokes of the L-shaped first section 26. The plurality of parallel-arranged second sections 27 join the first portion 26A of the first section 26, and separate from one another by a predetermined distance. The plurality of second sections 23 of the first electrode 21 and the plurality of second sections 27 of the second electrode 25 interdigitate in parallel. The second section 13 of the first electrode 11 in FIG. 1 is perpendicular to the second section 23 of the first electrode 21 in FIG. 2.
In Taiwan Patent No. 222,089 (hereinafter “the '089 patent”), a capacitor structure is disclosed, wherein the first section 12 of the first electrode 11 in the odd layer 10 and the first section 22 of the first electrode 21 in the even layer 20 are electrically coupled through a plurality of via plugs 14. Further, the first section 16 of the second electrode 15 in the odd layer 10 and the first section 26 of the second electrode 25 in the even layer 20 are electrically connected through a plurality of via plugs 18. By doing so, a capacitor structure spanning across several metal layers can be formed, wherein the first electrode 11 and the first electrode 21 together constitute the positive electrode, and the second electrode 15 and the second electrode 25 together constitute the negative electrode.
Although a multilevel interdigitated metal structure is already disclosed in U.S. Pat. No. 6,819,542, the electrical connection of the part of an electrode in the odd layer and the part of the same electrode in the even layer requires extra conducting wire structures, which results in wirings overly complicated. In U.S. Pat. No. 6,819,542, another multilevel interdigitated metal structure is disclosed, wherein the electrical connection of the part of an electrode in the odd layer and the part of the same electrode in the even layer is formed with via plugs. However, the positioning of via plugs is limited to the periphery of electrodes, which results in smaller unit capacitance.